Skip to content
Digital Design

Digital Design

This is an online textbook on digital design: how to describe hardware in SystemVerilog and build it on an FPGA. It is written for readers who can program but have not seen hardware before. It follows the lectures of UW CSE 369, Introduction to Digital Design, one chapter per lecture.

It is an unofficial study companion. It is not course material and is not endorsed by the course or its staff.

How this book was made, and how far to trust it

Section titled “How this book was made, and how far to trust it”

The text was written by AI language models, directed by the book's owner, and reviewed by separate AI agents that had not written the pages they reviewed. Most of those reviewers were the same kind of model as the writers; two outside reads were done by models from a different vendor. The chapter reviewers read each chapter against the course's lecture slides. No person who teaches the course has read it. Where this book and your lecture, section, lab handout or teaching staff disagree, the course is right.

What programs check. Truth tables, K-maps and state diagrams are computed from a written specification. Schematics are laid out by hand in a file, and a program checks what they compute against a specification. Waveforms are the recorded output of a simulation. Every SystemVerilog listing is a real file that open-source tools (slang, Verilator, Yosys and Icarus Verilog) process, and a listing meant to fail says so. The book has not been run in Quartus or ModelSim, which the course uses (Appendix A says more).

What those checks do not establish. They catch a figure that disagrees with its specification and code that a tool rejects. They do not catch a specification that misreads the problem, a sentence that describes a figure wrongly, a wrong explanation in a quiz, a block diagram marked as an illustration (no program checks what it computes or that its wires match the code it describes), or advice that holds for these tools and not for the course's. Reviewers did find false sentences on pages that had passed every program check. Those were corrected, and others may remain.

What is not written. Chapters 6 to 10 are not written yet. Nothing here covers timing constraints or bringing a button press into a circuit, and some pages in Chapters 3, 4 and 5 and in Appendix D point ahead to Chapter 6 for them. Those pointers lead to a chapter that is not written. For that material, use the course's own notes.

If you find a mistake, tell the person who gave you the book, with the page and the sentence. A page that a program has checked can still be wrong.

Chapters

Section titled “Chapters”
  • Chapter 1: Combinational Logic, follows Lecture 1 (Intro, Combinational Logic)
  • Chapter 2: Boolean Algebra and Verilog Basics, follows Lecture 2 (More Combinational Logic, Verilog Basics)
  • Chapter 3: Simulation, Hazards and Karnaugh Maps, follows Lecture 3 (Karnaugh Maps, Simulations)
  • Chapter 4: Arithmetic and Sequential Logic, follows Lecture 4 (Arithmetic, Sequential Logic)
  • Chapter 5: Finite State Machines, follows Lecture 5 (Finite State Machines)
  • Chapter 6: Timing Constraints and User Input, will follow Lecture 6 (Timing Constraints). Not written yet.
  • Chapter 7: Routing Elements, Registers and Counters, will follow Lecture 7 (Encoders, Decoders, Registers, Counters). Not written yet.
  • Chapter 8: Memory and Useful Doodads, will follow Lecture 8 (Memory, Useful Doodads). Not written yet.
  • Chapter 9: FPGAs, TTL and System Design, will follow Lecture 9 (TTL, Computer Components, FPGAs). Not written yet.
  • Chapter 10: Review and Wrap-up, will follow Lecture 10 (Quiz 3, so this chapter will be review material). Not written yet.

The appendices collect reference material. Appendices A, C and D are written; B and E are not yet.