Skip to content
Digital Design
Search
Ctrl
K
Cancel
Select theme
Dark
Light
Auto
Menu
Contents
1 · Combinational Logic
Chapter overview
1.1 What digital design is
1.2 Logic gates and truth tables
1.3 Three equivalent forms: circuit, expression, truth table
1.4 Combinational and sequential logic, and a first SystemVerilog module
2 · Boolean Algebra and Verilog Basics
Chapter overview
2.1 Boolean algebra
2.2 Sum of products and product of sums
2.3 Minimization goals and gate cost
2.4 DeMorgan's law and bubble pushing
2.5 Modules and signals in SystemVerilog
2.6 Signed numbers, buses, literals and concatenation
2.7 Hierarchy, always_comb and multiplexers
3 · Simulation, Hazards and Karnaugh Maps
Chapter overview
3.1 Testbenches
3.2 Reading waveforms and debugging
3.3 Gate delays and glitches
3.4 On sets, off sets and the uniting theorem
3.5 Building K-maps
3.6 Grouping and reading terms
3.7 Don't cares
3.8 Hazards and how to avoid them
3.9 Design examples
3.10 Review for Quiz 1
4 · Arithmetic and Sequential Logic
Chapter overview
4.1 Binary numbers and adders
4.2 Adders and parameters in SystemVerilog
4.3 Two's complement
4.4 Overflow and the adder/subtractor
4.5 Why circuits need state
4.6 Designing with registers, adders and muxes
4.7 Flip-flops and registers
4.8 Sequential logic in SystemVerilog
5 · Finite State Machines
Chapter overview
5.1 Timing controls in testbenches
5.2 State diagrams
5.3 From state diagram to circuit
5.4 The FSM design process: a vending machine
5.5 FSMs in SystemVerilog
5.6 Testing FSMs
6 · Timing Constraints and User Input
Chapter overview
7 · Routing Elements, Registers and Counters
Chapter overview
8 · Memory and Useful Doodads
Chapter overview
9 · FPGAs, TTL and System Design
Chapter overview
10 · Review and Wrap-up
Chapter overview
Appendices
Appendices overview
A. Tools and workflow
C. SystemVerilog reference
D. Notation and conventions
Select theme
Dark
Light
Auto
Chapter 6: Timing Constraints and User Input
This chapter is being written.