4.7 Flip-flops and registers

Why this matters

Every sequential circuit in this book is built from one part, the flip-flop, and every claim about when a circuit changes comes down to what a flip-flop does at a clock edge. If you know exactly when its output changes and when its input matters, you can read any waveform of a clocked circuit. Its behavior also explains why a clocked design can ignore most glitches.

Learning goals

State what a positive-edge D flip-flop does at a rising edge, what it needs from d around that edge, and what it does between edges.
Explain that a register is a row of flip-flops sharing one clock.
Contrast synchronous and asynchronous reset in their waveforms and in their structure.
Say what a zero-delay waveform shows and what it hides about a flip-flop's output delay.
Explain why a glitch on a flip-flop's input does not reach its output.

Intuition first

Intuition

A flip-flop is a camera with a very short exposure. It takes one photograph of its input d, at the instant the clock rises, and until the next rising edge it displays that photograph at its output q. Whatever d does between the photographs, a flicker, a change, a pulse, never shows at q, because nobody was looking.

The analogy has one limit: a real camera needs the scene to hold still for a moment around the exposure, and so does a flip-flop. That moment starts a short time before the edge and ends a short time after it, and it is the only time the input matters. Chapter 6 (not written yet) puts numbers on it. The book's waveforms are simulations, which squeeze the moment into a single instant; this section says how.

The flip-flop

Definition 4.7.1(positive-edge D flip-flop).

A positive-edge D flip-flop has a data input d, a clock input clk and an output q. At each rising edge of clk it samples d. For the sample to be reliable, d must hold one value for a short time before the edge, called the setup time, and for a short time after it, called the hold time. Together they make a window around the edge. If d is steady throughout that window, q takes that value, a short time after the edge, and holds it until the next rising edge. If d changes inside the window, the result is not defined. Outside the window d is ignored, so it may change freely.

The first waveform comes from simulating a flip-flop with a clock that rises at 20, 60, 100 and 140. The input d changes between the edges, once with a low pulse that is gone before the next edge.

Time in ps; one column is 10 ps.

Figure 4.7.1. One flip-flop sampling its input, in a simulation with no delays. d changes between the rising edges of clk, and q changes only at them.

Read Figure 4.7.1 from left to right. q is unknown, hatched, until the first rising edge, because the flip-flop has not taken any photograph yet. At that edge d is 0, so q becomes 0. d rises at 30, but there is no edge for a while, and q stays 0. At the edge at 60 d is 1, so q becomes 1. Then d falls at 70 and rises again at 90. That low pulse sits entirely between the edges at 60 and 100, and q never moves. At the edge at 100 d is 1 again, so q stays 1. When d falls at 110 and the next edge arrives at 140, q becomes 0.

Time in ps; one column is 10 ps.

Figure 4.7.2. The same flip-flop later in the run, with a short high pulse on d.

In Figure 4.7.2 the pulse is high, between the edges at 140 and 180: d rises at 150 and falls at 160. q stays 0 throughout, and at the edge at 180 it samples d = 0. A pulse on d that begins and ends between two rising edges is never seen at q. After the edge at 180, q is 1'd0.

In these waveforms q changes at exactly the instant of the rising edge. That is what a simulation with no delays shows: the simulations in the course give every logic delay a value of zero^{F (fact ch03/zero-delay-setup)}. A real flip-flop takes a short time after the edge before q shows the new value, called its clock-to-Q delay and written $t_\text{C2Q}$ (the slides also write $t_\text{clk-to-q}$ ). A zero-delay waveform cannot show it, and a later figure in this section adds it on purpose.

A simulation also has no window. It samples d at the instant of the edge, and it counts an input that the testbench writes with <= at the edge as changing just after it (Section 5.1 explains how the simulator orders this). So when a waveform in this book shows an input changing at a rising edge, the register is shown taking the value the input had before the edge. That is the simulator's idealization of the rule above: the window shrinks to a point, and the input moves just after it. In a circuit it is a fair picture of an input that another flip-flop on the same clock drives, because that flip-flop's output changes a clock-to-Q delay after the edge, provided the new value does not arrive before the hold time is over. Chapter 6 (not written yet) says when that holds. An input from outside the circuit, such as a push button, has no such promise: it can change inside the window.

Registers

Definition 4.7.2(register).

A register is a row of $n$ flip-flops that share one clock. Its input d and its output q are $n$ -bit buses, and the flip-flops sample their bits at the same rising edge. A 1-bit register is a flip-flop.

A 4-bit register is four flip-flops, and the tools count it that way: Yosys finds 4 storage bits in the module reg4_sync of this section, which has one 4-bit q. The count is in bits, not in cells: the four flip-flops are one cell, four bits wide.

Reset

A flip-flop starts out unknown, as the hatching in the figures shows. A reset drives it to a known value. There are two kinds, and they differ in when they act.

Definition 4.7.3(synchronous reset).

A synchronous reset is acted on only at a rising clock edge. At an edge where reset is 1, the register loads the value the design chooses for reset, instead of its normal next value. That value is often the constant 0, but it is whatever the design says: the starting state of a state machine, or the START of a down counter. The reset signal has no effect between edges. In its basic form it is a multiplexer in front of the d input, with reset as its select and the chosen value as the data input that is picked when reset is 1.

A design may also apply reset earlier in the logic that feeds the register, as the timer of Section 4.5 does. The register then loads whatever that logic produces while reset is 1: the timer loads 1, not 0. That is still a synchronous reset, because reset acts only through a register that samples at an edge. The value loaded should still be fixed. In the XOR register of Section 4.6 it is the input din, so that register is not put in a known state by its reset. That circuit shows where a reset multiplexer can sit, and it is not a reset to copy.

Definition 4.7.4(asynchronous reset).

An asynchronous reset acts at once. As soon as reset rises, q takes its reset value (0 in this book's examples), whether or not there is a clock edge. It is not a multiplexer in front of d: the flip-flop has its own reset input that overrides the clock.

Figure 4.7.3. A 4-bit register with a synchronous reset, drawn as a multiplexer in front of the register; the reset value here is 0. This drawing is simulated against the module reg4_sync.

To see the difference, the next simulation drives one flip-flop of each kind with the same clock, the same d (which stays 1) and the same reset. q_sync is the synchronous one and q_async is the asynchronous one. In the first figure reset rises and falls again between two rising edges.

Time in ps; one column is 10 ps.

Figure 4.7.4. A short pulse of reset between two rising edges, seen by a synchronous and an asynchronous flip-flop.

reset rises at 70 and falls at 90, and there is no rising edge of clk between those times: the edges are at 60 and 100. The synchronous flip-flop q_sync never looks at reset while it is 1, so it stays 1. The asynchronous flip-flop q_async does not wait: it falls to 0 at 70, when reset rises, and stays 0 after reset falls at 90, because nothing has loaded it. At the edge at 100 it samples d = 1 and becomes 1 again. After reset has fallen and before that edge, q_async was 1'd0, while q_sync was 1'd1.

Time in ps; one column is 10 ps.

Figure 4.7.5. A longer pulse of reset, high at a rising edge.

In Figure 4.7.5, reset rises at 150, between the edges at 140 and 180, and falls at 190. The asynchronous output falls at 150, at the instant reset rises. The synchronous one falls only at the edge at 180, where it sees reset = 1. After reset falls at 190, both outputs stay 0 until the edge at 220, where they sample d = 1 and both become 1.

So with a synchronous reset the register changes only at rising edges, which keeps every change in a design tied to the clock. That is why the book's designs use it.

In SystemVerilog

The flip-flops of this section are modules whose code Section 4.8 explains. This part of the section is about how a simulation can add delays to them, since a zero-delay waveform hides what a real flip-flop does just after the edge.

The timer of Section 4.5 has three parts on its feedback path: the multiplexer, the adder and the register. Here is a simulation-only model of it with a delay of 10 time units in each. It lives in a folder of delay models, since delays do not belong in a design: the book checks that the model and the zero-delay timer describe the same circuit.

// Simulation-only model of timer with a delay of 10 time units in every block: the multiplexer, the adder and the register.
module timer_delay(input logic clk, reset, output logic [3:0] sout, q);
  logic [3:0] b;

  assign #10 b = reset ? 4'd0 : q;
  assign #10 sout = b + 4'd1;

  always_ff @(posedge clk)
    q <= #10 sout;
endmodule

The assign #10 statements delay the multiplexer's and the adder's outputs by 10 time units, and q <= #10 sout makes the register's output change 10 time units after the edge. Both runs below use a clock period of 60 and the same stimulus: reset is 1 at the first edge and falls at that edge (the testbench writes it with <=, so, as above, the simulator counts it as falling just after the edge). First, with no delays:

Time in ps; one column is 10 ps.

Figure 4.7.6. The timer with no delays, from reset.

Everything that changes after a rising edge changes at the instant of the edge: at 30 q becomes 1, b becomes 1 and sout becomes 2, and at 90 they become 2, 2 and 3. Now the same run of the delay model. This is the one figure in this section that shows a flip-flop's output delay, and the numbers are not those of any real chip.

Time in ps; one column is 10 ps.

Figure 4.7.7. The timer with a delay of 10 in each block. After a rising edge, q changes first, then b, then sout.

Follow the chain in Figure 4.7.7. At the start b is unknown until 10, when the multiplexer's output becomes 0 because reset is 1. The adder then makes sout 1 at 20. The register takes sout at the rising edge at 30, but q changes only 10 later, at 40. At 30 reset falls, so the multiplexer starts passing q, which has no value yet, so b becomes unknown at 40, and sout at 50. At 40 q becomes 1, so b becomes 1 at 50 and sout becomes 2 at 60. Then everything is still, from 60 to the next edge at 90, which captures 2. After that edge q is 2 at 100, b at 110 and sout becomes 3 at 120, each 10 after the one before.

The idea behind the chain: the register's input, sout, is steady for most of every cycle, so it is steady in the window around each edge. The delays decide how long after an edge each signal takes to change, and two things can go wrong with them. If they are so long that sout is still changing when the window of the next edge begins, the register can capture a wrong value. If a change reaches a register's input so soon after an edge that it lands inside that edge's hold time, the register can also capture a wrong value, and a longer clock period does not help with that. Chapter 6 (not written yet) turns both into constraints.

Flip-flops hide glitches

In Section 3.3 the autopilot's output could glitch for a moment while its input moved through the gates. In a clocked design that blip is harmless, as long as nothing samples it. The circuit below puts a register on each input and on the output of the same request logic, with each gate delayed by 10 time units and the registers delayed by none.

// Simulation-only model of autopilot_reg: a delay of 10 time units in each gate of the request logic, and none in the registers.
module autopilot_reg_delay(input logic clk, CAR_in, PIC_in, PAR_in, output logic OUT);
  logic CAR, PIC, PAR, AE;
  logic A, B, C;

  always_ff @(posedge clk) begin
    CAR <= CAR_in;
    PIC <= PIC_in;
    PAR <= PAR_in;
  end

  not #10 g_a  (A, PIC);
  and #10 g_b  (B, CAR, A);
  and #10 g_c  (C, PAR, PIC);
  or  #10 g_ae (AE, B, C);

  always_ff @(posedge clk)
    OUT <= AE;
endmodule

Time in ps; one column is 10 ps.

Figure 4.7.8. The registered autopilot: AE glitches, OUT does not.

Here both requests, CAR and PAR, are 1 and stay there, as the lanes show. At the rising edge at 150 the pilot's input PIC_in falls (written with <=, so it counts as falling just after the edge). At the next edge, 210, the register PIC takes the new value and falls. The gates then respond as in Section 3.3: AE falls at 230 and rises again at 240, a glitch lasting one gate delay. But OUT, the register behind AE, takes AE only at rising edges, here at 150, 210 and 270. At 210 AE is still 1, and at 270 it has been 1 again since 240. So OUT never leaves 1. The glitch is gone before anyone looks.

This is the idea behind safe sequential circuits. The logic between two registers may glitch while no register is looking. What matters is that its output is steady in the window around each edge that captures it: settled before the edge (setup) and not changing again until the edge's hold time is over. The Lecture 4 slides call this a preview and say it returns a few weeks later^{F (fact ch04/glitch-preview-chapter6)}, and Chapter 6 (not written yet) makes it exact with setup and hold times.

Course conventions

How CSE 369 writes this

In CSE 369 code the reset is synchronous, active high and named reset, and the clock is clk. An asynchronous reset appears as an alternative and is not used in the course's designs. The timing names are $t_\text{setup}$ , $t_\text{hold}$ and $t_\text{C2Q}$ , and the delays of this section are labeled in the simulator's own time units, as Section 4.2 explained.

Pitfalls

Common pitfall

Drawing q following d between rising edges. The output changes only in response to a rising edge (a clock-to-Q delay after it, in hardware), and between edges it keeps the value it sampled.
Believing a pulse on d that falls between two edges is stored. If no edge sees it, q never does.
Expecting a synchronous reset to act the instant reset rises. It acts at the next rising edge at which reset is 1, and a pulse that ends before that edge does nothing.
Drawing a zero-delay waveform and concluding that q changes before the edge or exactly with it in real hardware. A real flip-flop's output changes a short time after the edge, which only a delay model shows.
Thinking that a register removes glitches by being slow. It removes the ones that stay clear of the window around the edge, because it looks at its input only there. A glitch inside the window can still get through.
Taking a waveform in which an input changes at the edge as proof that this is safe in hardware. A simulator treats the change as just after the edge. A circuit is safe only if the input is steady in the whole window, and an input from outside the circuit has no such promise.

Check your understanding

Take the quiz (4 questions)

In the first simulation, d falls and rises again between two rising edges while q is 1. What is q after the next rising edge?

d is back at 1 when the edge arrives, so the edge samples 1. The pulse in between is never seen.

reset rises and falls again between two rising edges, with d at 1. What does the asynchronous flip-flop hold after reset has fallen, and before the next edge?

It went to 0 as soon as reset rose, and nothing has loaded it since: it takes d only at the next rising edge. The synchronous flip-flop is the one that ignores such a pulse.

How many storage bits does the 4-bit register reg4_sync have, according to Yosys?

Apart from an asynchronous reset, what makes the output of a positive-edge D flip-flop change? A change on its d input. A rising clock edge: q shows the sampled value a clock-to-Q delay later, which a zero-delay simulation draws at the edge itself. Both the rising and the falling clock edge.

The rising edge samples d, and q follows after its clock-to-Q delay. A zero-delay waveform puts that change at the edge, and the delay model of this section shows the gap. A change on d alone never moves q, and the falling edge does nothing. An asynchronous reset is the one input that can change q without a rising edge.

Exercises

Exercise 4.7.1

The figure shows the clock and d for a stretch of a flip-flop's run. At the start q is 1. Work out q for the whole stretch.

Time in ps; one column is 10 ps.

Figure 4.7.9. The question: the clock and d.

Hint

At each rising edge, q takes the value d holds around that edge (here d changes only between edges, never at one). Between edges, q keeps its value.

Solution

Take the rising edges one at a time.

Edge at 140: d was 0, so q becomes 0.
d rises at 150 and falls at 160. There is no rising edge between them, so q stays 0.
Edge at 180: d was 0, so q stays 0.
d rises at 190. Edge at 220: d was 1, so q becomes 1.
d falls at 230. Edge at 260: d was 0, so q becomes 0.

Time in ps; one column is 10 ps.

Figure 4.7.10. The answer, from the simulation.

Tags: Warm-upWaveformsSequential logic

Exercise 4.7.2

The figure shows the clock, reset and d of the two flip-flops of this section for a stretch of the run. Before it, both flip-flops hold 1. Work out q_sync and q_async.

Time in ps; one column is 10 ps.

Figure 4.7.11. The question: the clock, reset and d.

Hint

The asynchronous output reacts to reset at once. The synchronous one reacts only at a rising edge, to the value reset had just before it. After a reset, both load d at the next rising edge where reset is 0.

Solution

Edge at 140: reset was 0 and d is 1, so both stay 1.
reset rises at 150. The asynchronous output falls at once, to 0. The synchronous output stays 1, because no edge has come.
Edge at 180: reset is 1. The synchronous output becomes 0. The asynchronous one stays 0.
reset falls at 190. Neither output changes, since a rising clk edge is needed to load d.
Edge at 220: reset is 0 and d is 1, so both become 1.
Edge at 260: reset is 0 and d is 1, so both stay 1.

Time in ps; one column is 10 ps.

Figure 4.7.12. The answer, from the simulation.

Tags: StandardWaveformsSequential logic

Exercise 4.7.3

A 4-bit register must keep its value unless a signal load is 1, and when load is 1 at a rising edge it takes d. Draw it from a 4-bit register and a multiplexer, and write the module.

Hint

The register captures its input at every edge. What must that input be, when load is 0, so that the register keeps its value?

Solution

At every edge the register takes whatever is at its input, so to keep its value the input must be its own output. A multiplexer in front of the register passes d when load is 1 and the register's output q when load is 0, and its select is load.

Figure 4.7.13. A register with a load input: the multiplexer chooses between d and the register's own output. This drawing is simulated against the module below.

// A 4-bit register that takes d only when load is 1, and otherwise keeps what it holds.
module reg4_load(input logic clk, load, input logic [3:0] d, output logic [3:0] q);
  always_ff @(posedge clk)
    if (load) q <= d;
endmodule

The module has an if with no else: in an always_ff block that means the register keeps its value, which is what the feedback wire of the drawing does. The simulation shows it.

Time in ps; one column is 50 ps.

Figure 4.7.14. The load register. q takes d only at a rising edge where load is 1.

Tags: StandardRegisters and countersSystemVerilog

Exercise 4.7.4

In the registered autopilot, suppose the register OUT is removed and the output is AE itself. What would the output do when the pilot hands over charge? Why does OUT not do it?

Hint

Look at when AE changes in the figure and when OUT looks at it.

Solution

Without OUT the output would be AE, which falls at 230 and rises again at 240, so it would show a glitch of one gate delay, although both requests stay on.

OUT looks at AE only at the rising edges. At 210 it sees 1, because the glitch has not started, and at 270 it sees 1, because the glitch ended at 240. The edges fall outside the glitch, so OUT stays 1. In this run the glitch, from 230 to 240, stays clear of the edges at 210 and 270. If a glitch fell inside the window around an edge, the register might capture it or might not, and the result would be undefined. Chapter 6 (not written yet) gives the size of the window.

Tags: StandardSequential logicHazards