Appendices

The appendices are for looking things up while you read a chapter or work an exercise. They teach nothing the chapters do not, and they say where to go for the details they leave out.

• A. Tools and workflow says which tools the course uses and which tools check the book, and shows how to compile, simulate and inspect a design with the open-source simulator Icarus Verilog. Quartus and ModelSim are covered only as far as the course's own slides and lab handouts state it, since the book has not run them; the course's own tutorials are the authority for those.
• C. SystemVerilog reference lists the part of the language the book uses: the four standard patterns, each construct with an example, the operator precedence, literals, where the checking tools disagree and what not to write.
• D. Notation and conventions lists how the book writes Boolean expressions, truth tables, K-maps, gates, state diagrams, waveforms and signal names, with the same figures the chapters use, and what other textbooks write for the same things.

Two appendices are not written yet and will appear later: a reference for the DE1-SoC board (Appendix B), and a collected list of common mistakes (Appendix E), assembled from the pitfalls of the chapters.

Like the chapters, the appendices were written and reviewed by AI models, and the home page says what that does and does not mean.