3.3 Gate delays and glitches

Why this matters

Until now a gate's output has changed the instant its input did. Real gates are not that fast, and the difference can matter: a circuit whose output should never change can still twitch for a moment while a change makes its way through the gates. This section shows where that twitch comes from, using a circuit that could matter a great deal, and how to work out when an output is first safe to trust.

Learning goals

Define propagation delay and say what a glitch is.
Draw the waveform of every net in a small circuit when each gate has its own delay.
Find a glitch in a delay waveform and explain which two paths cause it.
Work out how long after power-up an output first has a known value, from the gate delays.
Say why a zero-delay simulation cannot show a glitch.

Intuition first

Imagine two couriers leaving the same office at the same moment, one with the message "stop" and one with the message "go", each to the same warehouse, by different routes. If the stop courier arrives first, the warehouse is stopped for a while until the go courier arrives. Nobody did anything wrong, and the final instruction, go, is what was meant. But for the time between the two arrivals the warehouse was doing the wrong thing.

A circuit with two routes from one input to one output works the same way. Gates are the couriers: each takes a little time to turn a change at its inputs into a change at its output. If one input reaches the output by two routes of different length, the output can follow the short route's message first and the long route's message later. For a programmer, this is a race between two threads that read one shared value. The analogy breaks in this way: a circuit has no scheduler. Which route wins is decided by the delays of the gates on each route, not by chance in the program, but those delays differ from chip to chip.

Delay and glitches

Definition 3.3.1(propagation delay).

The propagation delay of a gate is the time between a change at one of its inputs and the resulting change at its output. In the models of this section each gate kind has a fixed delay. A gate whose delay is 0 passes a change to its output at the same instant.

Definition 3.3.2(glitch).

A glitch is a brief, unwanted change at the output of a combinational circuit while a change is still travelling through it. Usually the output leaves a value it should keep and returns to it a short time later; it can also change more than once on the way to a new value (Section 3.8).

A glitch is not a function of the circuit's truth table, which says only what the output is once everything has settled. It is a property of the timing. Section 3.8 returns to when a circuit can glitch and how to design one that cannot.

The autopilot circuit

Example 3.3.1(when the pilot hands over charge).

An autopilot has three inputs. CAR is a request from the copilot, PAR is a request from the pilot, and PIC says whether the pilot is in charge. The output AE says the autopilot is engaged. The rule is that the autopilot is engaged when whoever is in charge asks for it: $\mathrm{CAR} \cdot \overline{\mathrm{PIC}} +$ $\mathrm{PAR} \cdot \mathrm{PIC}$ . Three nets inside the circuit are named: pic_n is the inverted PIC, via_copilot is the output of the copilot's AND gate, and via_pilot is the output of the pilot's.

Only NOT, AND, OR gates (1 NOT, 2 AND, 1 OR). 4 gates in all.

Figure 3.3.1. The autopilot circuit. pic_n is the inverted PIC, via_copilot is the copilot's AND gate output and via_pilot is the pilot's.

Suppose both requests, CAR and PAR, are 1 and the pilot hands charge to the copilot, so that PIC falls from 1 to 0. Whoever is in charge, an autopilot request is on, so AE should be 1 before the change and 1 after. Now give every gate the same delay, and call it one gate delay. Follow the change from the moment PIC falls.

One gate delay later, the NOT gate has responded: pic_n rises. At the same moment the pilot's AND gate has responded to PIC alone: via_pilot falls.
One more gate delay later, the copilot's AND gate has seen pic_n rise, so via_copilot rises. At the same moment the OR gate, which saw via_pilot fall one delay ago while via_copilot was still low, responds, and AE falls.
One more delay later, the OR gate sees via_copilot high and AE rises again.

The output is 1, then 0 for exactly one gate delay, then 1. The route PIC to via_pilot to the OR gate is two gates long, and the route PIC to the NOT gate to via_copilot to the OR gate is three. The short route carries the message "the pilot's request no longer counts" two gate delays after PIC fell, and the long route carries "the copilot's request counts" a delay later. In between, neither request counts.

In SystemVerilog

The circuit, written without gate delays, is a module of four assignments. Its internal nets have the names used in the figure.

// Autopilot request logic. PIC says the pilot is in charge. The autopilot is engaged (AE) when the copilot
// requests it and the pilot is not in charge, or when the pilot requests it and the pilot is in charge.
module autopilot (
  input  logic CAR,   // copilot autopilot request
  input  logic PAR,   // pilot autopilot request
  input  logic PIC,   // pilot in charge
  output logic AE     // autopilot engaged
);
  logic pic_n, via_copilot, via_pilot;

  assign pic_n       = ~PIC;
  assign via_copilot = CAR & pic_n;
  assign via_pilot   = PAR & PIC;
  assign AE          = via_copilot | via_pilot;
endmodule

A testbench holds both requests high and lets PIC fall at time 60. The comments say that AE is 1 at the end of both steps.

// Testbench for autopilot with no gate delays: both requests stay high while the pilot hands over charge.
module autopilot_tb();
  logic CAR, PAR, PIC, AE;

  autopilot dut(.*);

  initial begin
    CAR = 1; PAR = 1; PIC = 1; #60;   // expect: AE=1
    PIC = 0;                   #60;   // expect: AE=1
    $stop;
  end
endmodule

Time in ps; one column is 10 ps.

Figure 3.3.2. The zero-delay simulation: the internal nets all move when PIC does, and AE never moves.

In Figure 3.3.2 PIC falls at time 60. At that same instant pic_n rises, via_copilot rises and via_pilot falls, because every gate responds with no delay. AE does not change. Within that one instant the simulator updates the nets one after another, but no simulated time passes between the updates, so nothing a waveform can show happens to AE. The section slides say that the simulations in the course give every gate a delay of zero.^{F (fact ch03/zero-delay-setup)} A simulation like this cannot show a glitch, because a glitch lives in the time between two gates responding, and here that time is zero.

To see the glitch, the simulation needs a delay for each gate. This book never puts delays in a design file: synthesis ignores them, and the hardware's real delays depend on the chip, not on the source code. The book keeps them in a separate file marked as a model for simulation only. Gate primitives take a delay after their name: not #10 g_not (pic_n, PIC); is a NOT gate with a delay of ten time units, named g_not, whose output is the first signal in the parentheses.

// Simulation-only model of autopilot with a delay of 10 time units in every gate.
module autopilot_delay (
  input  logic CAR,
  input  logic PAR,
  input  logic PIC,
  output logic AE
);
  logic pic_n, via_copilot, via_pilot;

  not #10 g_not     (pic_n, PIC);
  and #10 g_copilot (via_copilot, CAR, pic_n);
  and #10 g_pilot   (via_pilot, PAR, PIC);
  or  #10 g_engage  (AE, via_copilot, via_pilot);
endmodule

The book's tools check that this model computes the same function as the module above once everything has settled; they do not check that the glitch is the right size for any real chip. The testbench applies the same stimulus, then after PIC falls waits four steps of ten time units and a last step of twenty, with a comment on each line. A comment reads the output one time unit before its step ends, so the six comments see AE at times 59, 69, 79, 89, 99 and 119. They say AE is 1, 1, 1, 0, 1 and 1: the 0, read at time 89, is the dip.

// Testbench for the delay model of autopilot: the same stimulus as the zero-delay testbench, read every ten time units.
module autopilot_delay_tb();
  logic CAR, PAR, PIC, AE;

  autopilot_delay dut(.*);

  initial begin
    CAR = 1; PAR = 1; PIC = 1; #60;   // expect: AE=1
    PIC = 0;                   #10;   // expect: AE=1
                               #10;   // expect: AE=1
                               #10;   // expect: AE=0
                               #10;   // expect: AE=1
                               #20;   // expect: AE=1
    $stop;
  end
endmodule

Time in ps; one column is 10 ps.

Figure 3.3.3. The simulation with a delay in every gate: one column is one gate delay. The dip in AE is one column wide.

Read Figure 3.3.3 from left to right. PIC falls at time 60. One gate delay later, at time 70, pic_n rises and via_pilot falls. At time 80 via_copilot rises and AE falls. At time 90 AE rises again. So AE is 0 from time 80 to time 90, one gate delay, exactly what the hand trace said. At the left edge of the figure pic_n, via_copilot, via_pilot and AE start hatched: the simulator has no value for the output of a gate until one gate delay after enough of its inputs are known to decide it. pic_n and via_pilot become known at time 10, because the inputs are known from time 0. via_copilot becomes known at time 20, one delay after pic_n. AE is already known at time 20 as well, which is one delay after via_pilot. via_pilot is 1, and an OR gate with a 1 on one input is 1 whatever the other input is, so AE does not have to wait for via_copilot.

This dip belongs to this circuit, these delays and this direction of change. It is not something every circuit does, and it is not something this circuit does for every input change: Exercise 3.3.4 has PIC rising and uses the same gates and AE does not dip. Whether a circuit can glitch, and how to build one that cannot, is the subject of Section 3.8.

Suppose the NOT gate were twice as slow as the other gates, and PIC fell as before. What would happen to the dip in AE? It would disappear, because the pilot's AND gate would fall after the copilot's AND gate rose. It would get wider, because the copilot's route would take longer to deliver its message. It would stay the same, because the route through the pilot's AND gate is unchanged.

Course conventions

How CSE 369 writes this

The slides draw each waveform on its own grid, so every figure has to say what a column is. In this section a column is 10 time units, which is one gate delay in the autopilot figures; the exercises with mixed delays say how long each gate takes. The lecture's autopilot waveform gives every gate the same delay, drawn as one column of the grid.^{F (fact ch03/same-delay-lecture)} The practice problems give different gate kinds different delays in one circuit.^{F (fact ch03/mixed-delay-practice)} Read the delay of every gate, including any that is 0, before you draw anything.

Pitfalls

Common pitfall

Assuming a gate's output changes at the same instant as its input. Every gate takes a little time.
Looking for a glitch in a zero-delay simulation, or concluding from one that a circuit has none.
Treating the unknown values at the left edge of a delay simulation as a bug. They are there because nothing has reached the outputs yet.
Giving the sum of the delays along the longest path as the time an output is known, in every case. That sum is a limit that the output does not exceed, and a controlling input can make the output known sooner.
Drawing a delay waveform without writing down the delay of every gate first, including the gates whose delay is zero.

Check your understanding

Take the quiz (4 questions)

Exercises

Exercise 3.3.1

The autopilot circuit is rebuilt with a slower NOT gate. The delays are: NOT 20, AND 10 and OR 10 time units, and one column of the figure is 10. Both requests are high from time 0, and PIC falls at time 60. Draw pic_n, via_copilot, via_pilot and AE for the whole run, including the unknown values at the start.

Time in ps; one column is 10 ps.

Figure 3.3.4. The question: the inputs only.

Hint

Start from the unknown values: each net becomes known one delay of its gate after that gate's inputs are known. Then follow PIC's fall along both routes, one gate at a time.

Solution

Take each net in turn, in the order the signals reach them.

pic_n, the NOT gate: its input PIC is known from time 0, so pic_n is unknown until time 20 and is 0 from then on. PIC falls at 60, so pic_n rises at 80.
via_pilot, the pilot's AND gate: it is unknown until time 10, and then 1. PIC falls at 60, so via_pilot falls at 70.
via_copilot, the copilot's AND gate: its input pic_n becomes 0 at time 20, so via_copilot becomes 0 at time 30. pic_n rises at 80, so via_copilot rises at 90.
AE, the OR gate: via_pilot is 1 at time 10, so AE is 1 at time 20, even though via_copilot is still unknown. via_pilot falls at 70, so AE falls at 80. via_copilot rises at 90, so AE rises at 100.

Time in ps; one column is 10 ps.

Figure 3.3.5. The answer: every signal, from the simulation.

AE is 0 from time 80 to time 100, two columns, which is the delay of the NOT gate. The dip began when the pilot's route let go at time 80, and it lasted until the longer route through the NOT gate delivered, 20 later.

Tags: StandardHazardsWaveforms

Exercise 3.3.2

The circuit below has three gates with different delays: the AND gate 20, the NOT gate 10 and the OR gate 0, which means its output changes in the same instant as its input. All three inputs, P, Q and R, are 1 from time 0. How long after time 0 does G first have a known value, and what is it?

Only NOT, AND, OR gates (1 AND, 1 NOT, 1 OR). 3 gates in all.

Figure 3.3.6. The circuit of this exercise and the next.

Time in ps; one column is 10 ps.

Figure 3.3.7. The question: the inputs only.

Hint

Find when each gate's output becomes known, from the inputs towards the output. The OR gate has no delay of its own.

Solution

n1, the AND gate: known 20 after its inputs are known, so at time 20. With P and Q both 1, it is 1.
n2, the NOT gate: known at time 10. With R equal to 1, it is 0.
G, the OR gate, which takes no time: it needs both n1 and n2. n2 is 0 from time 10, which does not decide the OR, so G stays unknown until n1 is known at time 20. At time 20 G is 1, since n1 is 1.

So G is first known at time 20, which is the sum of the delays along the longest route, AND 20 plus OR 0.

Time in ps; one column is 10 ps.

Figure 3.3.8. The answer: every signal, from the simulation.

Tags: StandardWaveformsHazards

Exercise 3.3.3

The same circuit and delays as in the previous exercise, with P and Q equal to 1 as before, but now R is 0 from time 0. How long after time 0 does G first have a known value? Is it the same as before? Why or why not?

Time in ps; one column is 10 ps.

Figure 3.3.9. The question: the inputs only.

Hint

Which gate output becomes known first, and can its value decide the OR gate without waiting for the other input?

Solution

n2 is known at time 10, and with R equal to 0 it is 1. An OR gate with a 1 on one input outputs 1 whatever its other input is, so G is known at time 10, as soon as n2 is. The AND gate's output n1 does not become known until time 20, but G no longer needs it. So G is known at time 10, not at time 20.

Time in ps; one column is 10 ps.

Figure 3.3.10. The answer: every signal, from the simulation.

The sum of the delays on the longest route, 20, is a limit and not a prediction. Whether an output is known earlier depends on the input values: an input that decides a gate by itself, a 1 into an OR gate or a 0 into an AND gate, lets the output be known without waiting for the others.

Tags: ChallengeWaveformsHazards

Exercise 3.3.4

The autopilot circuit with one gate delay for every gate, as in the section. Now PIC starts at 0 and rises to 1 at time 60, with both requests high. Draw pic_n, via_copilot, via_pilot and AE. Does AE glitch?

Time in ps; one column is 10 ps.

Figure 3.3.11. The question: the inputs only.

Hint

Before time 60 the copilot is in charge, so via_copilot should be 1 and via_pilot should be 0. Follow the rise of PIC along both routes.

Solution

At the start, pic_n is known at time 10 and is 1, because PIC is 0. via_pilot is known at time 10 and is 0. via_copilot is known at time 20 and is 1. AE needs via_copilot, since via_pilot is 0 and does not decide an OR, so AE is known at time 30 and is 1.

PIC rises at time 60.

At time 70, one gate delay later, pic_n falls and via_pilot rises.
At time 80, via_copilot falls. AE has seen via_pilot rise and stays 1.
AE never changes.

Time in ps; one column is 10 ps.

Figure 3.3.12. The answer: every signal, from the simulation.

AE does not glitch. When PIC rises, the pilot's route raises the pilot's request before the copilot's route lowers the copilot's, so there is always one request on. With both requests high, the same circuit and the same delays glitch when PIC falls and not when it rises: the direction of the change matters.

Tags: StandardHazardsWaveforms