D. Notation and conventions

Textbooks disagree about notation, and a reader who moves between sources meets the same idea written four ways. This page lists every convention the book uses, shows it with the same figure component the chapters use, and says in the last column what you may also see elsewhere. The book's notation follows the lectures it accompanies, with a few choices of its own where the lectures vary or say nothing, each marked below as the book's choice. Where a lecture handout is inconsistent with itself, the book uses the form the lectures use.

The last column, You may also see, is background for reading other sources. Nothing on the site checks it, so treat it as a list of common alternatives and not as a survey. The figures in the other columns are drawn by the same components as the chapters' figures. The code forms are typed, and no program checks them against the figures.

Boolean expressions

Each entry gives the book's form, the form in SystemVerilog code, and what you may also see.

NOT. Book: $\overline{A}$ , a bar over the signal. Code: ~A. You may also see a prime (apostrophe) after the letter, a negation sign in front of it, or !A in programming-language style.
AND. Book: $AB$ , letters side by side. Code: A & B. Letters side by side is the book's choice for single letters; the lectures also write a dot between single letters. You may also see the symbol ∧.
OR. Book: $A + B$ , a plus sign. Code: A | B. You may also see the symbol ∨.
XOR. Book: $A \oplus B$ , a circled plus. Code: A ^ B. You may also see the symbol ⊻ in logic texts.
XNOR. Book: $\overline{A \oplus B}$ , a bar over an XOR. Code: ~(A ^ B). A bar over an XOR is the book's choice; the lectures name XNOR in words and in code, ~(a ^ b), but give it no symbol of their own. You may also see a dot inside a circle, or the symbol for equivalence.
NAND and NOR. Book: $\overline{AB}$ and $\overline{A + B}$ , a bar over the whole product or sum. Code: ~(A & B) and ~(A | B). You may also see, in logic texts, an up arrow between the letters for NAND (the Sheffer stroke) and a down arrow for NOR (the Peirce arrow).

Four details of the book's style matter when you compare pages.

A bar covers exactly what is under it. $\overline{AB}$ has one bar over the whole product, and $\overline{A}\,\overline{B}$ has a bar over each letter. They are different functions, and Example 1.2.1 shows both tables. The bars on this site are drawn from the parsed expression, so a bar always reaches as far as the parentheses in the source say.

AND is a dot when the names are longer than one letter. Letters written side by side would read as one name, so names such as the state bit and the input of a machine are separated by a dot: $\mathrm{PS}_{0} \cdot \mathrm{In}$ . For single letters the book writes $AB$ .

Multi-letter names stay whole. A signal called DBI or PBI is one signal, not a product of three. State bits are written $\mathrm{PS}_{1}$ and $\mathrm{PS}_{0}$ in math and ps[1] and ps[0] in code.

NOT never appears as a prime or as ~ in math. In code the operator is ~, and the book switches to the bar whenever it writes an expression as math. The expression language that the figures read is the code form, with the precedence given in Figure C.1, so what a figure shows is what the same text means in a testbench.

Vocabulary used throughout: CL is combinational logic and SL is sequential logic. A sum of products (SoP) is an OR of AND terms, and a product of sums (PoS) is an AND of OR terms. Lecture 2 points out that a sum of products is the disjunctive normal form (DNF) and a product of sums is the conjunctive normal form (CNF) of CSE 311.^{F (fact ch02/cse311-forms)} The on set of a function is the set of inputs where it is 1 and the off set is where it is 0. PS and NS are the present and next state of a machine, and DUT is the device under test, the module a testbench exercises (Section 3.1).

Truth tables

Inputs go on the left of a vertical rule and outputs on the right. Rows are in ascending binary order, with the first-listed input as the most significant bit, so for inputs A, B and C the rows run 000, 001, 010 and so on up to 111. A table with $n$ inputs has $2^n$ rows.

Truth table with 2 inputs (A, B) and outputs Carry, Sum; 4 rows in ascending binary order, A most significant
A	B	$\mathrm{Carry}$	$\mathrm{Sum}$
0	0	0	0
0	1	0	1
1	0	0	1
1	1	1	0

Figure D.1. The one-bit adder table. Rows are in ascending binary order with A as the most significant bit.

A don't care output is written X, in the output columns only. A table with don't cares looks like this one.

Truth table with 3 inputs (A, B, C) and output F; 8 rows in ascending binary order, A most significant; X means don't care
A	B	C	F
0	0	0	X
0	0	1	0
0	1	0	X
0	1	1	1
1	0	0	0
1	0	1	0
1	1	0	1
1	1	1	X

Figure D.2. A table with don't cares. An X marks an output the design may set either way.

This book	You may also see
Rows in ascending binary order, first input on the left is the most significant bit	the same order; some books also number the rows with minterm indices beside the inputs
Don't care written X	a dash, or the letter d
Inputs left of the rule, outputs right	the same, sometimes without a drawn rule

Karnaugh maps

The layouts below are the book's. Every map on the site is generated from a function, so the cells and the labels cannot disagree.

Four variables use columns for A and B and rows for C and D, with both axes in Gray order 00, 01, 11, 10, so that neighboring cells differ in one variable, including across the edges of the map.

Karnaugh map of F: columns AB, rows CD; cell values are 0, 1 or X for don't care
	AB=00	AB=01	AB=11	AB=10
CD=00	1	0	0	1
CD=01	0	1	1	0
CD=11	0	1	1	1
CD=10	1	0	0	1

Figure D.3. The four-variable layout: columns AB, rows CD, both in Gray order.

Three variables have a default layout, columns AB and row C, and an alternate layout, columns BC and row A. The book uses the default unless a page says otherwise.

Karnaugh map of F: columns AB, rows C; cell values are 0, 1 or X for don't care
	AB=00	AB=01	AB=11	AB=10
C=0	0	0	1	0
C=1	0	1	1	1

Karnaugh map of F: columns BC, rows A; cell values are 0, 1 or X for don't care
	BC=00	BC=01	BC=11	BC=10
A=0	0	0	1	0
A=1	0	1	1	1

Figure D.4. The same function in the default layout (columns AB, row C) and the alternate layout (columns BC, row A).

Two variables have columns for B and rows for A.

Karnaugh map of F: columns B, rows A; cell values are 0, 1 or X for don't care
	B=0	B=1
A=0	1	1
A=1	0	1

Figure D.5. The two-variable layout: columns B, rows A.

Labels. A map can carry bit labels, brackets, or both. A bracket marks where a variable is 1. With bit labels only, the value is read from the label; with brackets only, it is read from which side of the bracket a row or column lies on.

Karnaugh map of F: columns AB, rows CD; cell values are 0, 1 or X for don't care
	AB=00	AB=01	AB=11	AB=10
CD=00	1	0	0	1
CD=01	0	1	1	0
CD=11	0	1	1	1
CD=10	1	0	0	1

Figure D.6. The four-variable map with brackets only, no bit labels.

Groups. A group is a rounded outline around a rectangle of 1s, possibly including don't cares, whose width and height are powers of two. Groups may wrap around an edge, the four corners can form one group, groups may overlap, and each group is as large as it can be. The map is read group by group: each outline gives one product term, made of the variables that stay the same inside it. The description under every map on the site is generated from the groups, and a sentence in a chapter that says where a group is uses the same generator. For example, the cells of the four-variable map above where B and D are both 1 form a 2-by-2 square in rows CD=01 and 11, columns AB=01 and 11. Chapter 3 teaches grouping.

When a machine's next-state logic is mapped, the state bits go on the columns and an input on the rows, for example columns PS1 and PS0 and the row In.

This book	You may also see
Four variables: columns AB, rows CD	rows AB and columns CD, which is the same map turned on its side
Three variables: columns AB, row C (default)	columns BC, row A, which is the alternate layout above and the default of some books
Bit labels, brackets marking where a variable is 1, or both	bit labels only, or the cell's minterm number written in a corner

Gates and schematics

The gate symbols are the distinctive-shape ones: a curved back and a pointed front for OR, a flat back for AND, a triangle for NOT. A small circle, a bubble, means NOT and sits on an output or on an input. The seven gates are NOT, AND, OR, NAND, NOR, XOR and XNOR.

Figure D.7. NAND and XNOR: AND and XOR with a bubble on the output.

A bubble on an input inverts the signal as it enters the gate.

Figure D.8. Exclusive-or as a sum of products, drawn with bubbles on gate inputs.

Other symbols in the book's drawings: a multiplexer is a trapezoid with the data-input numbers written inside and the select on the slanted side, a bus is a line with a slash and its width, and no slash means one bit. A flip-flop or register is a box with d and q and a small triangle at the clock input. A box with a label inside, such as a comparator or an adder or a block named for what it does, is an operator or a part drawn without its inside.

Illustration a block diagram that explains an idea; its behavior is not checked

Figure D.9. A block diagram with a four-input multiplexer, a two-bit bus and two boxes drawn without their insides.

Illustration a block diagram that explains an idea; its behavior is not checked

Figure D.10. A register in a feedback path, drawn as a box with a clock triangle.

A drawing with a box in it is marked as an illustration on the site, because the inside of a box is not checked.

This book	You may also see
Distinctive-shape symbols with bubbles	rectangular symbols from the IEEE and IEC standard, with `&` and `≥1` written in the box
A bubble on an input or an output means NOT	an inverter drawn as a separate triangle gate on the wire
A bus is a slashed line with its width	a thick line, with the width written beside it
A multiplexer is a trapezoid with the data numbers inside	a rectangle labeled MUX

State diagrams

The book teaches Mealy machines first. A state is a circle with its name inside, an arrow is a transition, and the label on an arrow is the input over the output written with a slash: 1/0 means the input is 1 and the output is 0 while that arrow is taken. The start is marked by a thick arrow that comes from no state.

Figure D.11. A Mealy machine. Each label is input over output, and the thick arrow at the left marks the initial state.

With several inputs, the label is either a bit string in a declared input order or a product of literals, and the book says which order it uses. A Moore machine, whose output depends on the state only, writes the output inside the state circle instead. It appears in the book as a variation on the Mealy form.

This book	You may also see
Mealy first; arrow labels written input/output	Moore first, with outputs written inside the circles; the other order is also common
State names in the circles (`S0`, `S1`)	binary codes in the circles instead of names
Present state PS and next state NS	current state and next state, or Q and Q-plus

Waveforms and timing

A waveform lists the clock first, then the inputs, then internal signals, then the outputs. A bus is drawn as a box with its value written inside, in a radix the figure states. Fully unknown values are hatched and partly unknown buses are written bit by bit. A rising clock edge is marked when a figure is about sequential behavior. A state signal that is an enumeration shows the state names.

Time in ps; one column is 50 ps.

Figure D.12. The clock first, then the inputs reset and In, then the state, then the output.

How CSE 369 writes this

The time axis of a simulated waveform counts the simulator's time units, and the book's figures label it ps. Those numbers are arbitrary: they say nothing about how fast a real circuit is. The book says this once per chapter and does not repeat it, and this is that statement for this appendix.

Chapter 3 shows gate delay in waveforms. Section 4.7 writes the clock-to-Q delay of a flip-flop as $t_\text{C2Q}$ (the slides also write $t_\text{clk-to-q}$ ) and names $t_\text{setup}$ and $t_\text{hold}$ , which Chapter 6 is meant to put numbers on. That chapter is not written yet, so for the numbers use the course's own slides. In other books you may also see $t_{pcq}$ , $t_{su}$ and $t_h$ ; the course does not use them.

Signal and module names in book code

Item	Convention
Modules	lowercase words joined by underscores, and the file has the module's name
Testbench	the module's name followed by `_tb`, with no ports
Instance of the module under test	`dut`
Clock	`clk`
Reset	`reset`, synchronous and active high
Present and next state	`ps` and `ns`, both declared as the same enumeration
Enumeration constants	the state names of the diagram, such as `S0`
Declaration initializers	none in design files

The book's tools check several of these rules, among them the module and file name, the testbench name and its dut instance, one clock per design, and no initializers in design files. The remaining rows are habits of the book's own code.

The seven-segment decoder of Section 3.9 has an output bus leds in which bit $i$ drives segment L $i$ : L0 is the top segment, L1 the upper right, L2 the lower right, L3 the bottom, L4 the lower left, L5 the upper left and L6 the middle (see Figure 3.9.5). The decoder in that section is active high.

This book	You may also see
Segments named L0 to L6 starting at the top	letters a to g, with a at the top and the rest going clockwise, and g in the middle
`snake_case` module names	camel case or capitals, as in the lectures' own code (`DashboardController`, `MUX2`); equally legal
Synchronous reset in book code	an asynchronous reset named `rst_n` or `rstn`, active low

A table of every precedence rule the book uses for code is in Appendix C, which also lists the four standard patterns for modules and testbenches.